Day-to-Day Responsibilities
Write RTL (register transfer level) code in Verilog or VHDL to describe how a digital block behaves.
Work with the architecture team to define chip specifications for performance, power and area.
Build testbenches and run functional verification simulations to find bugs before fabrication.
Run logic synthesis to convert RTL code into a gate-level netlist built from standard cells.
Support physical design steps such as floorplanning, placement, clock tree synthesis and routing, using tools like Cadence Virtuoso.
Run sign-off checks such as Design Rule Check (DRC), Layout vs Schematic (LVS) and timing closure before tape-out.
Debug issues with post-silicon validation teams once fabricated chips return from the foundry.


