Day-to-Day Responsibilities
Read chip design specifications and write a verification plan that lists what must be tested
Build testbenches in SystemVerilog and UVM that drive inputs to the design and check its outputs
Run simulations and regressions on servers, and debug failures with the design team
Track functional coverage and write new tests to close gaps
Write assertions (SystemVerilog Assertions) and, where needed, use formal verification tools to prove design properties
Use Python, Perl or TCL scripts to automate regressions, log analysis and reports
Review bugs with designers and confirm when a block or chip is ready for tape-out


