Day-to-Day Responsibilities
Create the floorplan: decide where major blocks, memories, power grids and I/O pads sit on the chip.
Place standard cells and macros, balancing wire length, timing and routing congestion.
Build the clock tree so the clock signal reaches every flip-flop with minimal skew.
Route signal, power and clock wires, then fix noise, crosstalk and IR-drop issues.
Close timing using static timing analysis (STA), fixing setup and hold violations with the front-end design team.
Run physical verification checks such as design rule check (DRC) and layout versus schematic (LVS), then sign off the layout before tape-out.
Write Tcl and Python scripts to automate design flows and speed up repeated tasks.


