Day-to-Day Responsibilities
Translate chip micro-architecture specifications into RTL code in Verilog, SystemVerilog or VHDL.
Write and review synthesisable code for blocks such as memory controllers, bus interfaces, arithmetic units and peripheral logic.
Run simulations and debug waveforms with the verification team to find and fix functional bugs.
Run lint and clock domain crossing (CDC) checks and fix the issues they flag.
Work with synthesis engineers so the design meets timing, area and power targets, using constraints written by the design team.
Coordinate with DFT (design for test) and physical design teams so the block is testable and buildable.
Document design decisions, maintain block specifications and support FPGA prototyping where the project uses it.


